Buffers are used as a means for coupling internal circuitry of an integrated circuit (IC) device to external inputs and outputs. Buffer circuits may serve many purposes. For example, some input buffer circuits sense an incoming signal level and translate it to signal levels useful inside the device. For example, the signal levels for interfacing to one type of IC device known as transistor-transistor logic (TTL) are 0.8 volts for a "low" level and 2.0 volts for a "high" level. The signal levels used by another type of device known as complimentary metal-oxide-semiconductor (CMOS) are zero volts for a low level and a high level equal to the positive supply level, typically 5.0 volts. A TTL input buffer will translate between the TTL input levels and CMOS levels. Output buffer circuits may be used to boost the strength of the outgoing signals so that they can be transmitted over longer distances or drive greater current loads than can the internal circuitry of the IC device. For example, an output buffer circuit may be used to increase the signal strength of information coming from the output of a computer in order to drive that information down the length of an external cable to a connected printer. Without such a buffer circuit, the signal may not be strong enough to reach the printer.
Some buffer circuits are used to protect the IC device from damage from electro-static discharge (ESD). Static charge can build up on people and equipment handling the IC devices. This charge can be transmitted to the device through input and output pins of the devices. ESD protection circuitry is needed to deaden the destructive impact that a static charge may have on an IC device. ESD protection circuits are incorporated into input and output buffers and are placed across power supply lines of internal circuitry to protect the IC device from static charge build-up.
For demonstration purposes below, it is assumed that a low voltage is that voltage which corresponds most closely with one particular logical state, while a high voltage is that voltage which corresponds most closely with the opposite logical state in a binary scheme. For example, in a 5 volt CMOS system, a voltage greater than approximately 2.5 V may be considered a logical "1" and a voltage less than approximately 2.5 V may be considered a logical "0". Of course, this correspondence may be reversed such that a low voltage represents a logical "1" and a high voltage represents a logical "0". In an alternate system which operates with a 3 V supply, for example, a voltage greater than approximately 1.5 V may be considered a logical "1" and a voltage less than approximately 1.5 V may be considered a logical "0". Of course, this correspondence may again be reversed. In general, the lower supply voltage (which is simply ground in many applications) plus one half the difference between the upper supply voltage minus the lower supply voltage of any system may be considered the approximate boundary between high and low voltages or alternate logical states for demonstration purposes herein.
FIG. 1 illustrates a typical computer workspace set-up. In FIG. 1, notebook computer 100 is coupled to printer 101 through output line 104. In addition, printer 101 is coupled to computer 100 by input line 103. Generally, output line 104 and input line 103 are independent lines which exist within a single cable connecting computer 100 to printer 101. Also, as illustrated in FIG. 1, both computer 100 and printer 101 are independently plugged into power supply 102. As a result, turning off or unplugging computer 100 will have no effect on the power supplied to printer 101. In addition, output line 104 and input line 103 will remain electrically coupled to both computer 100 and printer 101 even when the power to computer 100 is shut off.
For most computer users, the completion of a work session is signified by either turning off computer 100 or by allowing computer 100 to go into sleep or deep power down mode. Most computer users do not turn off or unplug printer 101 because it is either inconvenient or impractical to do so, or because printer 101 is a community printer which if turned off by one user cannot be used by any others in the community. Furthermore, it is inconvenient or impractical to disconnect the cable containing output line 104 and input line 103 from the input/output (I/O) pins at the back of computer 100.
Therefore, as can be seen in FIG. 1, even if the power to computer 100 is shut off, or computer 100 is otherwise powered down, printer 101 can still parasitically operate computer 100 by supplying power to computer 100 through either input line 103 or output line 104. Such parasitic operation of computer 100 has caused significant problems in the past. One problem is damage to the internal circuitry of computer 100. In particular, there have been cases where the battery charging circuitry of a notebook computer has been severely damaged. A second problem that can occur in computer 100 is that certain circuits known as power-up circuits can become confused by the presence of a supply voltage through input line 103 or output line 104. Such confusion has been known to cause unpredictable behavior of computer 100 when it is powered back on. A third problem can occur with printer 101 when computer 100 is turned off. Supply voltages provided by printer 101 on lines 103 and 104 can be fed back into printer 101 as control signals. This can cause erroneous information to be fed back to printer 101, resulting in sporadic and unintentional operation of printer 101 including continuous printer initialization or page ejects. To understand how printer 101 can affect the internal circuitry of computer 100 through the pins coupled to input line 103 and output line 104, it is necessary to examine typical I/O buffers coupled to these pins within computer 100.
The circuit of FIG. 2a illustrates a typical output buffer used in computer 100. The output buffer of FIG. 2a is a conventional inverter circuit where the size of p-channel transistor 201 is very large as compared to standard minimum dimension inverters within the internal circuitry of the IC device. P-channel transistor 201 is scaled large in order to provide the necessary output drive and ESD protection for the IC as described below. Node 200 is the input to the output buffer circuit of FIG. 2a while the output is illustrated as node 203. Node 200 may be coupled to the more sensitive internal circuitry of the IC device from which the output buffer of FIG. 2a receives an input signal. Output node 203 may be coupled to an output pin such as the external pin of computer 100 to which output line 104 of FIG. 1 is attached.
Input node 200 is coupled to gate 207 of p-channel transistor 201 and to the gate of n-channel transistor 202. Output node 203 is coupled to the drain 205 of p-channel transistor 201 and to the drain of n-channel transistor 202. The supply voltage Vdd is coupled to the source 206 and the well 204 of p-channel transistor 201. Finally, the lower supply voltage Vss, which is usually ground, is coupled to the source and well (or substrate) of n-channel transistor 202. Note that Vdd not only supplies voltage to the output buffer of FIG. 2a, but also represents a power supply plane which may supply voltage to many other circuits within the IC, including, for example, circuits which control charging of the battery pack within a notebook computer system.
The power source Vdd, to the circuit of FIG. 2a is disengaged by turning off computer 100 of FIG. 1. However, it is possible for printer 101 to back-power the supply voltage node Vdd through output line 104 of FIG. 1 and into output node 203 of FIG. 2a. This unregulated, back-powered voltage through output node 203 up to the power supply plane of Vdd can travel through the power supply plane to the battery charging circuits of the computer, thereby causing damage to these circuits. To understand how a voltage at output node 203 of the output buffer circuit of FIG. 2a can be transferred up to the supply voltage node at Vdd, it is helpful to analyze the cross-section of p-channel transistor 201.
FIG. 2b is an illustration of the cross-section of p-channel transistor 201 illustrated in the output buffer circuit of FIG. 2a. As shown in FIG. 2b, output node 203 is coupled to the p-type drain 205 of p-channel transistor 201. Input node 200 is coupled to gate 207 of p-channel transistor 201 while Vdd is coupled to the p-type source 206 of p-channel transistor 201 as well as the n-type well tap 208 to n-well 204.
As can be seen in FIG. 2b, if a voltage is applied to output node 203 which is higher than Vdd, the pn junction comprising p-type drain 205 coupled to node 203 and n-well 204 coupled to Vdd will be forward biased. Therefore, current will flow through this forward biased diode from output node 203, into n-well 204, and then up through n-well tap 208 to Vdd. As a result, Vdd will be charged up to a voltage equal to the voltage at output node 203 minus the diode voltage drop between drain 205 and well 204. Coupling of output node 203 to the power supply plane of Vdd is beneficial for purposes of shunting an ESD event occurring at node 203 up to the Vdd plane in order to dissipate the static charge. However, such a configuration is not conducive for protecting internal circuitry of the IC coupled to Vdd, particularly in cases where output node 203 is back powered by an external device.
Note that the ESD protection performance of the circuit of FIG. 2a is improved by employing a large p-channel transistor 201 in order to minimize the resistance path seen by an ESD event between output node 203 and power supply plane Vdd. However, by scaling p-channel transistor 201 large enough to dissipate such an ESD event, this low resistance path between output node 203 and Vdd is similarly seen by a voltage supplied by an external device to output node 203. Thus, while increasing the size of p-channel transistor 201 aides the ESD protection properties of the circuit of FIG. 2a, increasing the size of transistor 201 also increases the likelihood that a peripheral device will back-power Vdd through output node 203 and cause damage to the IC or sporadic operation of the peripheral device.
What is desired is an output buffer circuit comprising large scale transistors to aid in ESD protection while isolating its power supply plane from its output node when the output node voltage is raised above Vdd. Such a buffer would be able to prevent damage to internal circuitry of the IC by preventing back-powering of Vdd through its output node from an active, peripheral device. cl SUMMARY OF THE PRESENT INVENTION
A CMOS buffer circuit is described which prevents a voltage applied at its input/output node from reaching its power supply plane, Vdd. The circuit comprises a CMOS inverter having a p-channel pull-up transistor and an n-channel pull-down transistor where the n-well in which the p-channel transistor resides is coupled to Vdd through a pn junction comprising the n-well and a source region of a second p-channel transistor coupled to Vdd. The second p-channel transistor is coupled to the source of the first pull-up p-channel transistor through its drain which is also coupled to the n-well. In one embodiment, the gate of this upper p-channel transistor is controlled by predriver circuitry which briefly turns on this p-channel transistor whenever the output node of the inverter switches from a low to a high state. This allows Vdd to briefly supply the output node in order to pull the output node all the way up to Vdd.
In another embodiment, the gate of the upper p-channel transistor is controlled by predriver circuitry which ensures that this p-channel transistor is turned on only when full power is applied to Vdd. This allows Vdd to be supplied to the second (lower) p-channel transistor so that the output node can be pulled all the way up to Vdd. The lower p-channel pull-up transistor of this inverter may be scaled large enough to dissipate an ESD event occurring at the output node, while a voltage applied to the output node is prevented from reaching the Vdd plane by reverse biasing of the pn junction. Such an output buffer may be incorporated into a computer system in order to prevent the internal circuitry of the computer system from being inadvertently powered up by a peripheral device coupled to the I/O pins of the computer system.